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A 5.25-GHz low-power down-conversion mixer in 0.18-μm CMOS technology

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Abstract

A 5.25 GHz low voltage, high linear and isolated mixer using TSMC 0.18 μm CMOS process for WLAN receiver was investigated. The paper presents a novel topology mixer that leads to better performance in terms of linearity, isolation and power consumption for low supply voltage. The measuring results of the proposed mixer achieve: 7.6 dB power conversion gain, 11.4 dB double side band noise figure, 3 dBm input third-order intercept point, and the total dc power consumption of this mixer including output buffers is 2.45 mW from a 1 V supply voltage. The current output buffer is about 2 mW, the excellent LO-RF, LO-IF and RF-IF isolation achieved up to 37.8, 54.8 and 38.2 dB, respectively.

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Acknowledgments

The authors would like to thank National Chip Implementation Center (CIC) for technical support, Taiwan, R.O.C.

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Authors and Affiliations

  1. Department of Electronic Engineering, National Kinmen Institute of Technology, University Rd., Jinning Township, Kinmen, 892, Taiwan R.O.C.

    Jun-Da Chen

  2. Graduate Institute of Integrated Circuit Design, National Changhua University of Education, Changhua, Taiwan

    Zhi-Ming Lin

  3. Department of Electrical Engineering, National Changhua University of Education, Changhua, Taiwan

    Jeen-Sheen Row

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  1. Jun-Da Chen
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  2. Zhi-Ming Lin
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Correspondence to Jun-Da Chen.

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Chen, JD., Lin, ZM. & Row, JS. A 5.25-GHz low-power down-conversion mixer in 0.18-μm CMOS technology. Analog Integr Circ Sig Process 62, 301–312 (2010). https://doi.org/10.1007/s10470-009-9347-1

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  • DOI: https://doi.org/10.1007/s10470-009-9347-1

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